1. Technology Field
The present invention relates to a storage system. More particularly, the present invention relates to a flash memory storage system applying a multi level cell (MLC) NAND flash memory as a storage medium, and a data writing method thereof.
2. Description of Related Art
With a quick developing of digital camera, cell phone camera and MP3, demand of storage media by customers is increased greatly. Since a flash memory has the advantages of non-volatile, energy saving, small size and none mechanical structure etc., it is suitable for portable applications, and especially for portable battery-powered products. For example, a solid state disk (SSD) is a storage device applying a NAND flash memory as a storage medium.
Generally, the flash memory of a flash memory storage system is divided into a plurality of physical blocks, and the physical blocks are grouped into a data area and a spare area. The physical blocks grouped within the data area are used for storing valid data written based on write commands, and the physical blocks of the spare area are used for substituting the physical blocks in the data area while executing the write command. To be specific, when the flash memory storage system receives the write command from a host for writing data into the physical block of the data area, the flash memory storage system selects a physical block from the spare area, and writes old valid data stored in the physical block of the data area to be written and new data into the physical block selected from the spare area, and further associates the physical block written with the new data to the data area. Moreover, the original physical block in the data area is erased and is associated to the spare area. To smoothly access the physical blocks storing data in an alternation approach, the flash memory storage system can provide logical blocks to the host. Namely, the flash memory storage system can establish a logical-physical address mapping table, and record and update a mapping relation between the logical blocks and the physical blocks of the data area for reflecting alternations of the physical blocks, so that the host can only perform writing to the provided logical blocks, and the flash memory storage system then can read data from or write data into the mapped physical blocks according to the logical-physical address mapping table.
However, with progress of a fabrication process of the flash memory, while a volume design of each physical block becomes greater, time spent on moving the aforementioned old valid data is comparatively increased, so that when the host executes the write command, a relatively long response time has to be waited. Particularly, when the flash memory storage system (for example, the SSD) applying a multi level cell (MLC) NAND flash memory as a storage medium is used as a main hard disk for a host system, the relatively long response time can seriously influence an operation performance of the host system. To resolve such problem, a dynamic random access memory (DRAM) is set in the flash memory storage system to serve as a cache memory. In such a structure, the host system can be notified that the flash memory storage system supports a cache accessing function. Therefore, data received from the host system is temporarily stored in the DRAM for accelerating the operation of the host. However, since the data stored in the DRAM is eliminated when the system is turned off or is substituted by a new data when a storage capacity thereof is insufficient, the host system can send a flush command to the flash memory storage system for indicating the flash memory system to immediately write the data temporarily stored in the DRAM to the MLC NAND flash memory, when the host system is about to be turned off or in case of a special demand. However, if the data temporarily stored in the DRAM is rather scattered, namely, the temporarily stored data belongs to different physical blocks, it takes a relatively long time to write the data of the DRAM to the MLC NAND flash memory. Now, the host system is in a wait state for waiting the flash memory storage system to accomplish the aforementioned operation, and such a delay time may cause an inconvenience for the user. Therefore, a system for accelerating accessing speed of the data temporarily stored in the DRAM is required to be developed in allusion to the storage system applying the MLC NAND flash memory.